Panmnesia Kicks off New Project to Redefine AI Infrastructure with Chiplets, Manycore Architectures, In-Memory Processing, and CXL

Overview of Panmnesia’s Solution Panmnesia, a company developing solutions for AI infrastructure, is set to receive $30 million in funding to carry out a project to revolutionize the architecture of AI data centers. As part of this effort, the company will develop chiplet-based modular accelerators that can accelerate large-scale AI services, including large-language models (LLMs), vector search, and recommendation systems. Time to Rethink Infrastructure for Modern AI Workloads5 Since AI services became increasingly integrated into our daily lives, model accuracy has emerged as a critical factor influencing user engagement and overall revenue. To improve accuracy, many companies continue to scale up their models and datasets. As these models and datasets grow rapidly, the infrastructure needed to support them is reaching unprecedented scales. The massive demand for computing and memory—often involving millions of GPUs in a data center—is driving 1. costs and 2.energy consumption to extreme levels. In addition, current AI infrastructures are suffering from 3. resource underutilization due to their reliance on GPUs—devices with a fixed ratio of computing and memory resources—without considering the diverse resource demands of different AI workloads. To overcome these challenges, AI infrastructure must evolve to become significantly more efficient in terms of cost, power consumption, and resource utilization. Project Overview Panmnesia aims to address the aforementioned challenges in AI infrastructure through the new R&D project. With $30M in support, Panmnesia plans to develop a next-generation chiplet-based AI accelerator and an integrated infrastructure system designed to efficiently support large-scale AI workloads. The accelerator can be configured in a flexible manner based on demands, and it also incorporates in-memory processing technology to minimize data movement. These components will be seamlessly integrated into Panmnesia’s proprietary CXL full-system solution. Concept Figure Representing Panmnesia’s Chiplet-based SoC. Technology Highlights Building on its existing expertise in memory and interconnect technologies such as CXL, Panmnesia is developing a next-generation system equipped with the following features to meet the demands of modern AI workloads: 1. Reusable and Flexible Chiplet-based Architecture Panmnesia’s AI accelerator consists of multiple chiplets, which serve as the building blocks of a system-on-chip (SoC). This chiplet-based architecture enables flexible scaling of compute and memory resources by placing compute and memory chiplets (also called as ‘tiles’) based on the demands of AI workloads, and it results in optimized resource utilization. In addition, this chiplet-based modular design allows for faster development cycles through partial SoC modification—only the chiplets related to the required functionality need to be updated, while the rest can be reused without any modification. This significantly reduces development time, thereby facilitating rapid adaptation to evolving industry trends. 2. Manycore Architecture and Vector Processor Panmnesia’s AI accelerator features two types of compute chiplets: (1) chiplets with manycore architecture (called ‘Core Tiles’) and (2) chiplets with vector processors (called ‘PE Tiles’). Therefore, customers can optimize performance per watt, by choosing appropriate compute chiplet architecture for their target workload. For instance, Core Tiles (chiplets with manycore architecture) are well-suited for accelerating highly parallel tasks exploiting its massive parallelism, while PE Tiles (chiplets with vector processors) are specialized for operations involving vector data formats, such as distance calculations. Moreover, it is able to integrate over a thousand cores within a chip, since the company is going to leverage advanced semiconductor process nodes to design its SoCs. Therefore, it is able to meet the massive computational demands of modern AI applications efficiently. 3. In-Memory Processing Data movement between memory resources and computational resources is one of the significant causes of power consumption. To solve this power issue, Panmnesia incorporates in-memory processing technologies to remove unnecessary data movement within AI infrastructure. This leads to significant reductions in power consumption associated with data transfers that occur during the processing of large-scale AI workloads. In addition to the development of new solutions, Panmnesia also integrates its proprietary CXL full-system solutions, such as CXL IP (intellectual property) into the system. As resource pooling based on CXL enables on-demand expansion of computing and memory resources, customers can optimize the cost of their AI infrastructure. Panmnesia’s Solution for Large-Scale AI A representative from Panmnesia stated, “We were able to secure this project thanks to the recognition of our existing expertise in memory and interconnect technologies, as well as our blueprint for revolutionizing AI infrastructure.” The representative added, “We expect this to be a cornerstone in developing unprecedented AI infrastructure solutions that will fundamentally transform data center architecture.”

Panmnesia Showcases High Fan-Out CXL 3.x Switch Solution at CXL DevCon 2025

Santa Clara, CA — April 30, 2025 — Panmnesia, a startup specializing in advanced link solutions for AI infrastructure, participated as an exhibitor at this year’s CXL DevCon, hosted by the Compute Express Link (CXL) Consortium. At the event held in Santa Clara, California, Panmnesia showcased its high fan-out CXL 3.x Switch–based framework designed for next-generation AI infrastructure and high-performance computing (HPC) systems. CXL 3.x Composable Server Built Based on Panmnesia’s CXL 3.x Switches CXL: A Key Enabler for the Efficient Construction of Next-Generation Data Centers As large-scale AI services become increasingly widespread, the importance of building computing infrastructure capable of operating these services efficiently is coming to the forefront. In this context, Compute Express Link (CXL), a high-speed interconnect technology, is gaining significant attention as a core enabler for next-generation computing infrastructure. CXL is attracting attention primarily for two key reasons: (1) reducing infrastructure deployment costs and (2) minimizing performance overhead. First, CXL enables pooling, which allows different types of system devices to be grouped and managed separately. When a particular type of device is insufficient, only the relevant resource pool—such as a memory pool or GPU pool—can be selectively expanded, thereby minimizing unnecessary resource waste and reducing infrastructure costs. Additionally, CXL-based systems guarantee cache coherency in a hardware-automated manner, which helps minimize overhead from memory management operations and redundant data copying, ultimately improving overall system efficiency. CXL DevCon 2025: Official Event by the CXL Consortium Amidst these technological trends, CXL DevCon 2025 was held as the official event organized by the CXL Consortium, offering a comprehensive view of the current state and future direction of the CXL ecosystem. The event featured product showcases from consortium members and invited talks from experts leading CXL standardization. After gaining attention at CXL DevCon 2024 for demonstrating interoperability of its CXL intellectual property (IP), Panmnesia returned this year as an exhibitor, presenting a framework built based on its high fan-out CXL 3.x Switches. Panmnesia’s Booth in Operation 1 Panmnesia’s Booth in Operation 2 Panmnesia's Exhibit: High Fan-Out CXL 3.x Switch–Based Framework Panmnesia’s CXL 3.x Switch SoC acts as a backbone interconnect, unifying diverse CXL devices into a cache-coherent system. The main benefits of this product can be summarized as follows: • Low Latency Developed based on Panmnesia’s proprietary low-latency CXL IP, the Switch SoC further reduces system latency by minimizing the average number of hops through its high fan-out structure, which allows more devices to be connected simultaneously. • Scalable & Flexible Architecture The switch supports multi-level switching, allowing multiple switches to be connected across hierarchical layers, as well as port-based routing (PBR), which enables flexible system topology—including both the physical connection structure and data routing paths—based on device port IDs. It also supports connections to all types of system devices—including CPUs, GPUs, and memory modules—making it ideal for constructing large-scale systems in various configurations to meet specific application needs. At the exhibition, Panmnesia showcased a CXL 3.x Composable Server consisting of multiple CXL-enabled server nodes interconnected via Panmnesia’s CXL 3.x Switch. Each node featured disaggregated CPU, GPU, and memory resources powered by Panmnesia’s CXL IP. This composable architecture enables dynamic system configuration based on workload demands, helping to reduce infrastructure costs. Using this framework, Panmnesia demonstrated how CXL can accelerate AI and HPC workloads—including retrieval-augmented generation (RAG), large language models (LLMs), and scientific simulations—attracting strong interest from other CXL technology companies. Panmnesia’s Technical Presentation on CXL DevCon 2025 Panmnesia’s Technical Presentation At the event, Dr. Yongjin Cho, Executive Vice President of Panmnesia, delivered a technical presentation highlighting the capabilities of Panmnesia’s CXL 3.x Switches. He introduced example solutions enabled by the technology and shared real-world use cases of CXL 3.x Switch–based infrastructure. Dr. Cho also participated in in-depth discussions with other CXL Consortium members regarding ecosystem development. As the only company to deliver a session addressing CXL 3.x Switch technologies, Panmnesia drew interest from specialists exploring next-generation architectural solutions. Panmnesia’s Logo Displayed During CXL DevCon 2025 “In CXL DevCon 2025, we received numerous inquiries from attendees—many of whom were exploring CXL 3.x Switch deployments for the first time,” said a company representative. “We look forward to expanding collaboration with partners to help advance the CXL 3.x ecosystem,” the representative added. This content has also been featured in the following article. Business Korea

Panmnesia Unveils Solution to Minimize AI Infrastructure Costs by Replacing Redundant GPUs Into Memory Expanders – Winner of the CES 2025 Innovation Award

Panmnesia’s Booth CXL fabless startup company Panmnesia participated in CES 2025, the world's largest electronics trade show, held in Las Vegas, USA, from January 7 to 10. At the event, Panmnesia garnered significant attention by showcasing its CES Innovation Award-winning product, the ‘CXL-based GPU Memory Expansion Kit’. This product allows to build a cost-effective AI infrastructure while minimizing performance overhead through the employment of Panmnesia’s CXL 3.1 IP. Several companies who work with AI infrastructure showed a significant interest on the Panmnesia’s CXL solution during the exhibition. CES 2025 Innovation Award Winner : Panmnesia’s CXL-based GPU Memory Expansion Kit Components of Panmnesia’s CXL-Based GPU Memory Expansion Kit Overview of Panmnesia's Exhibits at CES 2025 Panmnesia participated in CES 2025, the International Consumer Electronics Show organized by the Consumer Technology Association (CTA). With over 50 years of tradition, this prestigious event brings together leading global companies and innovative startups to showcase next-generation technologies. This year, CES 2025 attracted over 150,000 attendees and more than 4,000 companies, facilitating a exchange of technological innovations. Panmnesia showcased the ‘CXL-based GPU Memory Expansion Kit’, based on its key product, CXL 3.1 IP, at this exhibition. This innovative solution consists of CXL-GPUs and CXL-Memory Expanders. It can increase GPU internal memory capacity from tens of gigabytes to terabytes. By leveraging this solution, users can significantly reduce the costs required for building AI infrastructure. Large-scale AI services, such as generative AI, have become an integral part of modern life. However, these applications often require memory capacities exceeding several terabytes (10^12 bytes), far surpassing the memory capacity of GPU devices, which is about tens of gigabytes (10^9 bytes). To address this gap, server operators often deploy numerous GPUs in their AI infrastructure. While this approach helps meet memory demands, it comes with significant cost burdens, making it a less feasible solution for many organizations. Panmnesia has developed a solution leveraging its proprietary CXL IP to address this challenge. Users can deploy GPUs based on their computational workload needs. If additional memory capacity is needed, they can simply attach a CXL-Memory Expanders (which is highly memory-intensive), instead of adding more GPUs. This approach allows users to replace redundant GPUs used for traditional GPU memory expansion into Memory Expanders, thereby minimizing waste of computational resources and significantly reducing AI infrastructure costs. Panmnesia’s CXL 3.1 Controller IP : The World First Two-Digit Nanosecond Latency Core of Panmnesia’s Solution : The Low-Latency CXL IP The cost efficient memory expansion of Panmnesia’s CXL-based GPU Memory Expansion Kit is made possible by the design based on Panmnesia's proprietary technology, CXL 3.1 IP. By connecting CXL-Memory Expanders to CXL-GPUs via CXL, an integrated memory space is created. The embedded CXL IP automatically handles memory management operations for this unified memory space. As a result, the GPU can access the memory space of Memory Expanders using simple load/store intsructions, just as it did to access its internal memory. This creates the illusion of an expanded GPU system memory capacity for users. Additionally, since Panmnesia has optimized the latency of their CXL 3.1 IP, the memory expansion shows the minimized performance overhead while reducing AI infrastructure costs. Panmnesia’s CXL 3.1 IP has achieved the industry’s first double-digit nanosecond latency, which is about three times shorter than that of other vendors’ products. Panmnesia’s CES 2025 Innovation Award Trophy Panmnesia’s CXL-Based GPU Memory Expansion Kit on CES Innovation Award Booth Two Consecutive Years of Winning the CES Innovation Award At CES 2025, Panmnesia was honored with the prestigious CES Innovation Award for its CXL-Based GPU Memory Expansion Kit, marking its second consecutive win at the global event. The CES Innovation Award is given by the CTA(Consumer Technology Association) to products with excellent technology and innovation among global innovation products. A panel of over 100 industry experts meticulously evaluates the entries based on their technicality, functionality and originality as well as the potential benefits these technologies can provide to humanity. Panmnesia’s Booth at CES 2025 Panmnesia’s CXL-Based GPU Memory Expansion Kit Panmnesia has made headlines by winning the CES Innovation Award for two consecutive years in the field of AI-focused CXL solutions. After being recognized at CES 2024 for its 'CXL-enabled AI accelerator', the company secured another win at CES 2025 with its ‘CXL-Based GPU Memory Expansion Kit.’ To date, Panmnesia remains the only company to earn back-to-back awards in this sector (CXL solution for AI). A representative from Panmnesia expressed their excitement, stating, "We are thrilled to have our CXL 3.1 IP recognized for its technical excellence and innovation by the expert panel from the CTA, marking our second consecutive CES Innovation Award." Panmnesia’s Booth 1 Panmnesia’s Booth 2 Panmnesia’s Booth 3 Panmnesia’s Booth 4 Panmnesia’s Booth 5 At CES 2025, numerous IT representatives and investors from global companies, including hyperscalers and server manufacturers, visited Panmnesia’s booth. A representative from Panmnesia stated, “Our GPU Memory Expansion Kit, in particular, has drawn significant attention from companies in the AI data center sector, thanks to its ability to efficiently reduce AI infrastructure costs.” The representative added, “We aim to strengthen relationships with the companies we met during the exhibition, as well as with our existing clients currently involved in discussions and collaborations.” Additionally, we will focus on expanding our customer base among AI semiconductor companies and small-to-medium data center operators. By doing so, we will strive to become global pioneers in data center interconnect technology. For more information on the CXL-Based GPU Memory Expansion Kit that Panmnesia exhibited at CES 2025, please refer to the following link. Panmnesia’s Booth 6 Panmnesia’s Booth 7 CXL-Based GPU Memory Expansion Kit Video CES 2025

Panmnesia Unveiled the World’s First Rack-Scale CXL Solution Including CXL 3.1 Switches at SC24

The CXL fabless start-up Panmnesia unveiled the ‘CXL 3.1 Composable Server’, a HPC server solution based on the CXL 3.1 Switch, at SC24, the largest supercomputing exhibition held last month in Atlanta. The company stated that various server operating and manufacturing companies showed a lot of interest in the product. Panmnesia’s Booth Panmnesia's CXL 3.1 Composable Server Overview of Panmnesia’s Exhibit at the SC24 Panmnesia participated in SC24 exhibition, the largest annual event about supercomputing. During the event, global supercomputer operators and related technology development institutions such as the DoE (US Department of Energy) and HPE (Hewlett Packard Enterprise) present their latest technologies. In this year’s event, more than 18,000 people attended the event to see the latest technologies. Panmnesia showcased its rack-scale server solution for HPC (High-Performance Computing), which has been built with its main products, CXL 3.1 IP (Intellectual Property) and CXL 3.1 Switches, at this exhibition. This solution includes CXL-Enabled Compute Nodes and CXL-Enabled Memory Nodes, allowing for flexible adjustment of the number of compute nodes and memory nodes to accommodate user requirements. The existing HPC systems simply increase the number of servers to secure memory capacity when memory resource is insufficient for running large-scale scientific simulations. Since typical servers employ a monolithic architecture, which combines computing and memory resources within each server, there was a problem of having to purchase additional computing resources while adding a server to secure memory capacity. Panmnesia's solution transforms the landscape entirely. The company’s CXL 3.1 Composable Server is divided into nodes dedicated to computing and memory resources —referred to as CXL-Enabled Compute Nodes and CXL-Enabled Memory Nodes, respectively. To meet customer’s requirements, resources can be selectively scaled by adding nodes dedicated to the required resource (i.e., compute/memory resource). This approach eliminates unnecessary resource waste, the company representative explained. Example Configurations of Panmnesia CXL 3.1 Switch-Based Composable Server The Core of Panmnesia's Solution: CXL 3.1 Switch and CXL IP The system can be flexibly configured by connecting multiple nodes of different types, as previously mentioned, thanks to Panmnesia’s two main products: CXL 3.1 IP and CXL 3.1 Switch. At first, CXL Switch is a device connecting multiple CXL devices. Panmnesia’s CXL 3.1 Switch stands out for its ‘high scalability’, allowing hundreds of devices to be connected, and its 'general connectivity' supporting connections to various CXL devices , including memory, accelerators, and CPUs. This enables the connection of numerous nodes with diverse devices, in any desired configuration. Meanwhile, Panmnesia's CXL IP allows multiple connected devices to build an integrated memory space. Since Panmnesia's low-latency CXL IP performs a series of management operations on this integrated memory space in a hardware-automated manner, users can access the memory space quickly and with minimal overhead. Demonstration: Scientific Simulation Acceleration on the Multiphysics Framework Panmnesia also offers a CXL-enabled software stack based on the Linux OS, running on CXL 3.1 hardware. At this exhibition, the company integrated the Multiphysics framework—a program commonly used by HPC users for running various scientific simulations —into its CXL-enabled software stack. This allows users to leverage the benefits of the CXL system while running simulations on the Multiphysics framework as they did before, without needing to modify their code (i.e., application/simulation code). “As a result, we have confirmed that it is possible to reduce the execution time of scientific simulations, one of the most common applications of HPC, by about 44%,” the representative said. Panmnesia’s Booth 1 Panmnesia’s Booth 2 Panmnesia’s Booth 3 Panmnesia’s Booth 4 Additional Activities of Panmnesia Panmnesia also exhibited its CXL 3.1 server solution at the CXL Pavilion booth. The CXL Pavilion is operated by the official CXL consortium, which selects 10 companies worldwide each year to showcase the latest CXL technologies. This year, a total of 16 companies, including industry leaders such as Intel, AMD, Teledyne LeCroy, and Viavi, were selected to participate, alongside Panmnesia. Presentation by Panmnesia's Executive Vice President, Yongjin Cho, at the Exhibitor Forum In addition to this, Panmnesia engaged in various external activities during the SC event. At the SC Exhibitor Forum, Panmnesia's Executive Vice President, Dr. Yongjin Cho, introduced the company’s CXL 3.1 server solution and its example usages. Dr. Cho also proceeded face-to-face meetings with several global companies based in Americas and Europe, following up on prior discussions. Panmnesia's CXL Pavilion Booth 1 Panmnesia's CXL Pavilion Booth 2 Panmnesia's CXL Pavilion Booth 3 Panmnesia's CXL Pavilion Booth 4 The Panmnesia representative commented, "Various global companies, including Google, Microsoft, AWS, Oracle, Dell, Supermicro, Gigabyte, Nokia, Intel, and AMD, visited our booth at this year's SC24 exhibition. In particular, several server operators and server manufacturers showed strong interest in Panmnesia's CXL 3.1 solution." The representative continued, “It was a valuable event that enabled us to gain a deeper understanding of customers’ needs across various aspects, including required features, architecture, and timelines, through discussions with companies that operate or manufacture large-scale servers, and expand our customer pool.” The representative also noted, “We imagine a future where their servers are equipped with CXL 3.1 Switches produced by Panmnesia.” Panmnesia's CXL 3.1 Composable Server For more information on the CXL 3.1 Composable Server that Panmnesia exhibited at SC24, please refer to the following link. A video explaining Panmnesia's CXL 3.1 Composable Server

CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP

Panmnesia, a South Korean fabless CXL startup, announced that it has successfully secured over $60M in Series A funding. The valuation of the company exceeds $250M. This represents the largest Series A venture capital investment to date for any fabless startup headquartered in South Korea. With this latest round, Panmnesia has successfully raised more than $80M totally in cumulative investment, a mix of private and public funding, within approximately two years since its founding. Panmnesia’s CEO, Myoungsoo Jung, stated that the funds from this round will be used to complete key projects, including the manufacturing of the CXL 3.1 Switch silicon chip, advancement of CXL IP, and collaboration with global IT companies. Team Panmnesia Panmnesia: A Startup Leading CXL Solutions Panmnesia, which successfully secured Series A funding, is a fabless startup developing solutions for efficient memory expansion. Although the company has various product lineups, such as solutions for data centers and AI, Panmnesia is currently focusing on developing semiconductor IP (Intellectual Property) and switch chips for CXL (Compute Express Link), the next-generation memory interconnect technology. Panmnesia was founded in 2022 by CEO Myoungsoo Jung, a tenured professor at KAIST, along with master’s and Ph. D. researchers from KAIST. Since then, the company has welcomed many young engineers and experienced professionals from global semiconductor companies to collaborate on the development of advanced CXL products. Driven by its memory expansion technology, which has been in development since 2015, Panmnesia has experienced rapid growth and recently leveraged this momentum to successfully complete its Series A funding. Panmnesia’s Key Milestones An Unprecedented Scale of Series A Investment During the Venture Capital Freeze The current investment climate is notably challenging. According to a report from CrunchBase , the first quarter of this year marked the second-lowest global startup funding quarter since 2018. Furthermore, KPMG highlighted that global VC investments in Q3 2024 reached their lowest point in seven years. In these challenging conditions, Panmnesia's recent Series A funding round stands out as a remarkable achievement, raising over $60M solely through VC investment. A total of 15 venture investment institutions participated in this Series A funding, led by InterVest and joined by new investors such as Korea Investment Partners, KB Investment, Woori Venture Partners, BSK Investment, Nvestor, Murex Partners, Daesung Private Equity, and TS Investment. Existing investors, including Daekyo Investment, GNTech Venture Capital, SL Investment, TimeWorks Investment, Quantum Ventures Korea, and Yuanta Investment Korea, also participated in this round. Notably, Daekyo Investment and Quantum Ventures Korea expressed strong confidence in Panmnesia’s steady growth by making their largest investment since their founding. A representative from the Korean investment market remarked, “This is the largest VC funding I’ve seen in this field. Notably, in this Series A round, approximately half of Korea's top ten venture investment institutions by assets under management (AUM) participated simultaneously. This is an exceptional case that underscores the investment industry’s strong interest in Panmnesia.” Example Architecture That Can Be Built with Panmnesia’s CXL Solutions. Reasons Behind Successful Investment Attraction: ‘Leading CXL Technology’ Panmnesia identified ‘world-leading technology’ as the primary reason for its successful fundraising. Panmnesia’s technology has always been associated with the term ‘world's first.’ This began when Panmnesia introduced the world’s first CXL full-system framework including the CXL Switch, at the 2022 USENIX Annual Conference. More recently, at the OCP/OpenInfra joint event, the company once again surprised the industry by unveiling the world's first CXL 3.1 IP with two-digit nanosecond latency and the world’s first CXL-GPU. Panmnesia also put much effort into validating and advancing its CXL solutions. For instance, during a keynote speech last July, the company revealed the silicon-proven CXL 3.1 controller chip as a demonstration of these efforts. Nowadays, Panmnesia is collaborating with global IT companies by utilizing its advanced CXL solutions. A Panmnesia representative commented, “The success of this fundraising round was made possible because investment institutions recognized and highly valued Panmnesia's globally leading CXL technology.” Panmnesia’s CXL 3.1 IP - 1 Panmnesia’s CXL 3.1 IP - 2 Panmnesia’s CXL 3.1 Switch Utilization Plan for Series A Funds Regarding the utilization of funds from this investment round, CEO Jung stated, “We will allocate the investment to successfully complete key projects, such as manufacturing of the high-bandwidth CXL 3.1 Switch silicon chip, advancement of next-generation CXL IP, and collaboration projects with global IT companies. I hope that everyone participating in this journey will be recognized and receive attention as a main contributor to the unprecedented success.”

CXL Fabless Startup Panmnesia to Unveil World’s First CXL-Enabled AI Cluster Including CXL 3.1 Switches at The 2024 OCP Global Summit

Panmnesia, a Korean fabless startup that develops CXL switch SoCs and CXL IP, will present the world's first CXL-enabled AI cluster featuring CXL 3.1 switches at the 2024 OCP Global Summit. The OCP Global Summit, which Panmnesia is attending this year, is hosted by OCP, the world's largest data center hardware development council. During the event, relevant global companies discuss solutions for building a cost-effective and sustainable data center IT infrastructure. At this year's event, which is particularly focused on AI-related topics, Panmnesia will be seeking to expand its global customer base by unveiling a demonstration of its CXL-enabled AI cluster to accelerate RAG, a next-generation AI application utilized in services such as ChatGPT. Intensifying AI Competition Highlights the Necessity of “CXL” In light of the growing importance of AI services, companies are striving to enhance the quality of their AI services. In recent years, there have been repeated attempts to achieve higher accuracy, especially by increasing the size of AI models or utilizing more data. This has led to an increased demand for memory in enterprises. To increase memory capacity, enterprises added more servers in general. However, the addition of further servers resulted in unnecessary expenditure for companies, as they are required to purchase a range of server components beyond the memory itself. This is where CXL (Compute Express Link), the next generation of connectivity, comes in. In contrast to the previous method, CXL offers a new way to expand memory. With CXL, companies just need to purchase the memory and the CXL device, rather than spending money on additional server components. As a result, CXL is attracting significant interest from major IT companies that have suffered from the costs associated with inefficient memory expansion. Panmnesia: A Startup Leading CXL Solutions for AI While CXL is gaining global attention, Panmnesia, a fabless startup, has also attracted significant interest in the industry for its leadership in the development of CXL technology. Panmnesia first garnered attention by introducing the world's first full system framework "DirectCXL" with CXL 2.0 switches at the 2022 USENIX Annual Technical Conference. Panmnesia further solidified its leadership in CXL technology by unveiling the world’s first system that includes all types of CXL 3.0/3.1 components at the 2023 SC (Supercomputing) Exhibition. Furthermore, Panmnesia announced innovative CXL solutions to accelerate AI in response to industry demand. First, at the Flash Memory Summit (FMS) 2023, Panmnesia demonstrated the acceleration of recommendation systems, one of the most commercially used AI applications, on their CXL 3.0/3.1 framework. Subsequently, at CES 2024, Panmnesia won the CES Innovation Award for announcing a CXL-enabled AI accelerator that reduces data movement overhead by processing data close to memory. Most recently, at the OCP/OpenInfra Summit this year, Panmnesia introduced CXL-GPU, a solution that expands GPU system memory through CXL technology, further solidifying Panmnesia's position as the leader of CXL solution for AI. Panmnesia to Unveil CXL-Enabled AI Cluster At the 2024 OCP Global Summit, Panmnesia will showcase the CXL-enabled AI Cluster, which represents the cutting edge of the company's AI-focused CXL technology. The CXL-enabled AI cluster comprises a "CXL-Memory Node" equipped with CXL memory expanders, and a "CXL-GPU Node" equipped with CXL-GPUs. The CXL-Memory Node provides large memory capacity through multiple CXL memory expanders, while the CXL-GPU Node accelerates AI model inference/training via numerous CXL-GPUs. To construct this AI cluster, Panmnesia employed its two main products: the CXL IP and the CXL switch. Firstly, Panmneia's CXL IP is embedded in each system device to enable CXL functionality. Since the CXL IP optimizes the communication process among the devices, it allows for memory expansion without sacrificing performance, all while remaining cost-effective.Next, Panmnesia’s CXL 3.1 switch is used to interconnect various types of devices aforementioned. Note that this involves more than just physical connections. Specifically, CXL categorizes accelerators such as GPUs as Type 2 devices and memory expanders as Type 3. In order to interconnect these different types of devices together, the switch must support the features required by each type of device. Since Panmnesia's CXL 3.1 switches meet these requirements, it is able to configure the CXL-enabled AI clusters consisting of different types of devices. In addition, Panmnesia’s CXL 3.1 switches play a crucial role in enhancing scalability across multiple nodes (servers). This is achieved through support for CXL 3.1 features designed for high scalability, such as multi-level switching and port-based routing. "This is the world's first AI cluster featuring CXL 3.1 switches and also the world's first complete system with CXL-GPU, an AI acceleration solution powered by CXL," a company representative stated. The CXL 3.1 switch chips will also be available to customers in the second half of next year. Panmnesia’s Demonstration: Acceleration of RAG, a Cutting-Edge AI Model, on CXL-Enabled AI Cluster At the OCP Global Summit, Panmnesia is bringing up the world's first demonstration of Retrieval-Augmented Generation (RAG) acceleration on their innovative CXL-enabled AI cluster. RAG is a next-generation LLM (large-scale language model) currently under development and in use by various companies such as OpenAI and Microsoft. It could become a major application in the industry nowadays, as it addresses the inherent limitations of existing LLMs, namely the hallucination phenomenon. To briefly explain the concept of RAG, it searches for information related to the user's input in a database containing a vast amount of data and uses the search result to improve the accuracy of the LLM's response. "Our demonstration will show that Panmnesia’s CXL-enabled AI cluster can accelerate all stages of the RAG application, by utilizing various types of CXL devices,” said a Panmnesia representative. According to Panmnesia's explanation, the searching process can be efficiently accelerated by the large memory expanded through CXL, while CXL-GPUs accelerate the LLM. "Our CXL 3.1 switches and high-performance CXL IP allow us to connect dozens or even hundreds of devices, effectively accelerating the latest AI applications like RAG at the data center level," said an official at Panmensia. "Through our participation in the OCP Global Summit, we aim to strengthen our existing global partnerships and expand our customer base.", the official added. Panmnesia will be showcasing its CXL-enabled AI cluster and demonstrations at booth C64 at the 2024 OCP Global Summit, taking place from October 15th to 17th in San Jose, California, USA. OCP Global Summit Trailer Video

Panmnesia to Offer CXL 3.1 Switch Chips Next Year - Unveils Product Roadmap

In the middle of this month, Panmnesia CEO Myoungsoo Jung revealed the development status and roadmap for their core CXL product line. Panmnesia plans to produce the CXL 3.1 switch SoC chip and provide it to customers by the second half of next year. It will incorporate Panmnesia’s groundbreaking IP, boasting the world’s first sub-two digit nanosecond latency for CXL designs. Emerging Memory Expansion Solution in the AI Era: Compute eXpress Link (CXL) In recent years, the widespread adoption of large-scale machine learning services like ChatGPT has significantly impacted daily life. As companies behind these advanced services push for higher performance by expanding model sizes and data volumes, the demand for memory capacity in data centers has surged. In this context, major tech companies are increasingly focusing on Compute eXpress Link (CXL), an interconnect technology that offers cost-effective memory expansion with both economic and performance benefits. CXL enables the integration of computing and memory resources in any desired proportion, creating a unified memory space that facilitates efficient memory expansion. Additionally, CXL controllers handle operations such as cache coherence management through hardware acceleration, making it a performance-optimized choice. Panmnesia has emerged as one of leading companies in the CXL technology landscape, first garnered attention at the 2022 USENIX Annual Technical Conference by unveiling the world’s first complete CXL 2.0 system, including CXL switches. In the following year, Panmnesia advanced this system to support the CXL 3.0 and CXL 3.1 standards, showcasing these advancements at international exhibitions. Earlier this year, Panmnesia introduced a CXL-enabled AI accelerator, earning the CES 2024 Innovation Award. Recently, the company has attracted significant media and industry attention by unveiling a CXL-GPU solution that expands GPU system memory using CXL. Panmnesia Unveils CXL Product Roadmap Featuring CXL Switch SoC and CXL IP In the middle of this month, Myoungsoo Jung, CEO of Panmnesia, delivered a speech detailing the development status and future roadmap for Panmnesia’s core CXL product lines including the CXL switch SoC (System-on-Chip) and CXL IP. During his presentation, Jung announced plans to provide the CXL 3.1 switch chip to customers by the second half of next year. The CXL switch is a pivotal device that connects various system components such as CPUs, memories, and accelerators, managing end-to-end communication between them. This product is currently under intensive development, leveraging Panmnesia’s proprietary IP. Panmnesia’s CXL switch supports all features defined in the latest CXL 3.1 standard and is fully interoperable with devices adhering to previous standards. It offers high scalability by allowing multiple switches to be connected in multiple levels or configured in a fabric-like structure, enabling the connection of hundreds of devices across multiple servers. Adiitionally, since Panmnesia’s IP covers all subprotocols of CXL, including CXL.mem, CXL.cache, and CXL.io, their switch is highly versatile, capable of connecting various types of devices such as memory, AI accelerators, and GPUs. Thanks to its high scalability and versatility, Panmnesia’s CXL switch is ideal for connecting a wide variety of devices in large-scale servers, such as those used in cloud environments. In the latter part of the presentation, CEO Jung unveiled the actual silicon of the CXL 3.1 controller chip, which completed the silicon manufacturing process earlier this year. Holding up the chip, Jung explained, “This silicon chip incorporates Panmnesia’s high-performance CXL 3.1 IP.” Notably, Panmnesia’s CXL 3.1 IP achieved the world’s first sub-two digit nanosecond latency. This IP will also be integrated into the CXL switch chip developed by Panmnesia. CEO Jung expressed confidence in the product, stating, “Our CXL 3.1 switch will not only reduce server operating costs but also enable practical memory expansion in terms of performance, thanks to our high-performance CXL IP.” For more detailed information about Panmnesia’s CXL solutions, visit their official website or the Design & Reuse platform, which mediates the sale of semiconductor IP. Design & Reuse

CXL-GPU: Panmnesia Breaks The Limitation of GPU Memory Capacity with World's First Two-Digit nanosecond Latency CXL Controller

Panmnesia revealed world’s first two-digit nanosecond latency CXL Controller, featuring its own CXL ASIC IP. The latency is shorter than any other reported values. Panmnesia’s CXL IP could be applied to various system devices to realize cost-efficient memory expansion with high performance. As a usage example of the CXL IP, Panmnesia introduced a storage expansion solution named ‘CXLGPU’, that can supply terabytes of memory to the GPU. Panmnesia will unveil this technology at USENIX federated conferences and ACM HotStorage, held in Santa Clara in July. CXL: Key for the Cost-Efficient Memory Expansion The memory requirement in data centers increases as large-scale applications such as large language models (LLM) become more common in our lives. To expand memory capacity costefficiently while maintaining reasonable performance, many big tech companies are focusing on an interconnect technology called Compute Express Link (CXL). With CXL, it is possible to construct a scalable, integrated memory space by connecting multiple system devices. Since memory resources or computational resources can be added independently based on demand, CXL enables memory expansion with minimized TCO (total cost of ownership). Furthermore, users do not need to manually manage the integrated memory space, as the CXL controller handles a set of memory management operations (e.g., cache coherence management) in a hardware-automated manner. Panmnesia’s CXL Controller with Two-Digit Nanosecond Latency: Key Component for a Truly Efficient CXL System Although CXL appears to be a promising solution for efficient memory expansion, one challenge remains to meet customers' expectations: latency. Customers expect memory expansion without a significant performance drop compared to local memory access, making it crucial to minimize the additional latency caused by memory expansion. Recently, Panmnesia developed a memory expansion technology that meets the customer’s demand for low latency. Panmnesia has developed and completed the silicon manufacturing process of their CXL Controller IP, which executes all of CXL’s communication operations with low latency. A CXL Controller featuring Panmnesia’s CXL IP exhibits the two-digit nanosecond round-trip latency, which is shorter than any other reported values. A representative at Panmnesia stated that “It was able to achieve such low latency by fully optimizing the controller's operations across all relevant layers, including the physical layer, link layer, and transaction layer.” The CXL controller IP developed by Panmnesia can be applied to a wide range of system devices, such as CPUs, switches, accelerators, and memory expanders, to automate and accelerate a set of memory management operations. By doing this, customers will be able to realize their ideal memory expansion, which reduces TCO with minimal performance degradation. CXL-GPU: Application of Panmnesia’s High-Speed CXL Controller IP While latency optimization is a common requirement across various industries, it is particularly important for companies providing AI services, such as LLM and recommendation systems. This is because latency directly impacts user satisfaction and revenue generation of AI services. As an example usage of the low-latency CXL Controller IP, Panmnesia introduces ‘CXL-GPU,’ a GPU storage expansion solution that can increase the memory capacity of the GPU while optimizing the latency of AI service. This solution constructs a terabyte-scale memory space by connecting multiple storage devices via CXL and integrates it into the GPU memory space. Data and model parameters for large-scale AI services can be stored in this integrated memory space, allowing the GPU to access and process this data for AI services. Panmnesia’s low-latency CXL controllers handle memory management operations while being deployed in both GPU and storage devices. Unlike the traditional method of purchasing multiple high-end GPUs to secure memory capacity, Panmnesia’s CXL-based storage expansion solution minimizes the server construction costs for AIservices since it enables the selective addition of memory resources based on demands. Furthermore, Panmnesia’s low-latency CXL controller minimizes the overhead caused by memory expansion, thereby maintaining reasonable performance. Panmnesia has built the hardware prototype of CXL-GPU by integrating their CXL Controller IP with custom GPU, which has been developed based on an open-source framework. Evaluation results on this prototype show that Panmnesia’s CXL-GPU solution outperforms traditional GPU memory expansion solution by 3.23 times. “The GPU storage expansion solution based on our CXL controller IP would help AI-service providers to significantly reduce their server construction cost,” said Dr. Myoungsoo Jung, CEO of Panmnesia. “While we introduced the solution to expand GPU memory capacity, our low-latency CXL controller IP is also a key component for efficient memory expansion in cloud computing and HPC.” CXL-GPU, Panmnesia’s GPU storage expansion solution using their CXL controller IP, will be unveiled at USENIX federated conferences and ACM HotStorage, held in Santa Clara in July. For more information on Panmnesia and its technologies, please refer to the following links. Tom's Hardware [link] MSN [link] Yahoo Tech [link] Digitaltrends [link] Storage Newsletter [link] Medium [link] Embedded [link] WCCFTECH [link] ThinkComputers [link] OC3D [link] TechPowerUp [link] DiskManufacturer [link] Gigazine [link] WhatPSU [link] Aroged [link] TweakTown [link] Techspot [link] Blocks & Files [link] Read The Technical Report Download The PDF Information about CXL 3.1 Controller IP (Design and Reuse)

Panmnesia Demonstrated Interoperability of its CXL IP at The Inaugural CXL DevCon Exhibition

Panmnesia participated as the main sponsor at the inaugural CXL Consortium Developer Conference 2024 (CXL DevCon 2024), held from April 30th to May 1st in Santa Clara, California, USA. Panmnesia showcased the interoperability of its Compute Express Link (CXL) IP at the event. On the second day, Panmnesia's Chief Strategy Officer (CSO), Miryeong Kwon, presented state-of-the-art CXL switch-based solutions for next-generation data centers. CXL: Promising Solution for The Next-Generation Datacenters Big tech companies have recently been racing to build large AI models. The demand for AI accelerators and memory expansion devices continues to surge with the evolution of larger and more complex AI models. To address this need, the industry is turning to CXL technology. CXL is a next-generation interface technology connecting various system devices while automating a set of behaviors required for memory management (cache coherency management). This technology optimizes the performance and efficiency of the data center by enabling flexible scaling of memory according to the resource requirements. This flexibility offers high performance and competitive prices, catching the eye of global tech giants like Microsoft and Meta. This CXL technology continues to evolve practically with each iteration of the specification. Since the proposal of CXL 1.0 in 2019, CXL 2.0 specification, utilizing CXL switches to improve scalability, was introduced in the following year. CXL 3.0/3.1 specifications were announced in 2022 and 2023, supporting memory sharing among multiple users to maximize memory resource utilization. Currently, various global companies are focusing on establishment of the CXL ecosystem, which requires verifying interoperability between different system device manufacturers to ensure compliance with CXL specifications. CXL DevCon 2024: The Inaugural Exhibition Officially Hosted by CXL Consortium The first-ever CXL DevCon 2024 is a event for global CXL consortium member companies that develops new products utilizing CXL technology. CXL DevCon 2024 featured exciting CXL technology demonstrations, presentations covering numerous important CXL topics, and opportunities to network with industry peers. In this inaugural exhibition, representative companies in CXL industry including Panmnesia, Samsung, SK Hynix, and Teledyne LeCroy participated as main sponsor. As one of the companies leading the CXL industry, Panmnesia showcased its innovative technology, and presented CXL use case scenario at CXL DevCon 2024. Panmnesia Exhibits: CXL Interoperability Test Demo and CXL All-in-One Framework At CXL DevCon 2024, Panmnesia demonstrated the interoperability of its CXL IP. Specifically, the demo showed that the CXL-enabled device implemented with Panmnesia’s CXL IP interacts with CXL-enabled CPUs from major CPU vendors, all in strict accordance with the CXL protocol. The validation of interoperability was conducted using the CXL test platform provided by a global test solution provider. An official from Panmnesia stated that they are planning to attend an official CXL compliance test event in the near future, to prove the functionality of its CXL IP product which not only supports all features of the latest version of the CXL specification but also maintains backward compatibility with previous versions. In addition to the interoperability test demonstration, Panmnesia also exhibited its CXL all-in-one framework. The CXL all-in-one framework consists of CXL CPUs, switches, memory expansion devices, and software based on Panmnesia’s CXL IPs. This framework features a full array of both hardware and software components meticulously designed for robust development processes. Panmnesia explained that the CXL all-in-one framework supports all vital features of CXL 3.1, such as multi-level switches and memory sharing capabilities, enabling the delivery of multiple terabytes of memory, and maximizing memory utilization. Panmnesia CSO’s Presentation at CXL DevCon: Next-Generation CXL Switch-Based Solutions On the second day of CXL DevCon, Miryeong Kwon, Panmnesia’s Chief Strategy Officer (CSO), presented Panmnesia's next-generation CXL switch-based solution. The CXL switch is a pivotal component of the CXL system, as it enables flexible connection of system devices according to user specifications. Panmnesia has meticulously designed its CXL switch to incorporate sophisticated software known as the fabric manager to enable configurable connectivity. This versatile feature allows users to scale their CXL system effortlessly. "Panmnesia's CXL switch technology will be crucial for optimizing the efficiency of big data services such as generative AI," said Miryeong Kwon. "Following CXL DevCon 2024, Panmnesia will participate in the Open Compute Project (OCP) meeting at Meta's Sunnyvale campus to unveil our CXL switch solutions. The event will be attended by executives and engineers from global IT companies, such as Intel, AMD, Micron, HPE, Marvell, Samsung, and SK Hynix. We look forward to showcasing our innovative technology and vision at the meeting.", she added. You can find more detailed information about CXL DevCon exhibition at the link below. CXL DevCon 2024